A flash memory is a non-volatile storage device that can be electrically erased and reprogrammed. Flash memories are commonly used in memory cards, USB flash drives and solid-state drives for general storage and transfer of data between computers and other digital products. Flash memory devices typically store information in an array of memory cells made using floating gate transistors.
A floating gate transistor is a field effect transistor having a structure similar to a conventional MOSFET (metal oxide semiconductor field effect transistor). Floating gate MOSFETs are distinguished from conventional MOSFETs because the floating gate transistor includes two gates instead of one. In addition to an upper control gate, a floating gate transistor includes an additional floating gate beneath the control gate and above the transistor channel but completely electrically isolated by an insulating layer such as an oxide layer that completely surrounds the floating gate. This electrically isolated floating gate creates a floating node in DC with a number of inputs or secondary gates such as the control gate, formed above the floating gate and electrically isolated from it. These secondary gates or inputs are only capacitively connected to the floating gate. Because the floating gate is completely surrounded by highly resistive material, i.e. the insulating layer, any charge placed on the floating gate is trapped there and the floating gate remains unchanged for long periods of time until the floating gate MOSFET is erased. Unless erased, the floating gate will not discharge for many years under normal conditions. Fowler-Nordheim Tunneling or other Hot-Carrier injection mechanisms may be used to modify the amount of charge stored in the floating gate, e.g. to erase the floating gate. The erase operation is therefore critical to the operation of floating gate transistors.
The default state of an NOR (“Not Or” electronic logic gate) flash cell is logically equivalent to a binary “one” value because current flows through the channel under application of an appropriate voltage to the control gate when charge is stored in the floating gate. Such a flash cell device can be programmed or set to binary “zero” by applying an elevated voltage to the control gate.
To erase such a flash cell, i.e. resetting it to the “one” state, a large voltage of the opposite polarity is applied between the control gate and the source causing electrons to exit the floating gate through quantum tunneling. In this manner, the electrical charge is removed from the floating gate. This tunneling necessarily takes place through the inter-gate dielectric formed between the floating gate and the control gate. It is therefore important to provide a floating gate transistor having a floating gate and an inter-gate dielectric with appropriate shapes and thicknesses that will promote the creation of a strong electric field that enables tunneling and allows for the flash cell device to be erased.
One conventional method for forming the inter-gate dielectric includes locally oxidizing an exposed portion of polysilicon that will form the floating gate, the localized portion being an exposed portion of polysilicon hot covered by an oxidation resistant film such as silicon nitride. This thermal oxidation of polysilicon includes a high thermal budget, which is generally undesirable in CMOS (Complimentary Metal Oxide Semiconductor) technology. It would therefore be desirable to form floating gate transistors utilizing a lowered thermal budget.
In split gate flash cell technology, a common drain is typically formed in the substrate between two adjacent floating gate transistors. The common drain is commonly formed between the control gates of adjacent floating gate transistors and misalignment issues associated with patterning the control gate material can result in the common drain being improperly positioned and the control gates of adjacent floating gate transistors having different lengths. This is especially undesirable as this results in different channel lengths of the floating gate transistors and therefore different operational characteristics of the transistors.
Conventional split gate flash cells, adjacent floating gate transistors using a common drain and methods for making the same are therefore beset with a number of limitations and shortcomings.